Qualcomm's Tenstorrent Talks, Optical CHIPS Act Funding, and Agentic Chip Design

Three semiconductor developments this week define the architecture of AI's hardware future: Qualcomm's reported $8–10B acquisition talks for Tenstorrent (Jim Keller's Tensix/RISC-V inference chip startup) would combine Qualcomm's global manufacturing scale with Tenstorrent's sparse-attention LLM silicon and bypass Arm licensing; the US Department of Commerce's $50M CHIPS Act grant to Coherent Corp. for InP photonic wafer capacity in Sherman, Texas directly addresses the copper-wire bandwidth wall inside AI GPU clusters; and SigmanticAI's launch of a "Cursor for chip design" — an agentic multi-agent system for Verilog RTL generation and closed-loop EDA verification — could compress custom ASIC design from years to weeks.

---

🔌 Qualcomm-Tenstorrent Acquisition — RISC-V Enters the Datacenter

The Strategic Gap Qualcomm Is Trying to Fill

Qualcomm is the world's leading mobile chip designer (Snapdragon) with dominant positions in:

• Smartphone SoCs (42% market share)
• Automotive silicon (Snapdragon Ride)
• On-device AI NPUs (Hexagon NPU in Snapdragon 8 Elite)

But Qualcomm has no competitive datacenter AI product. Its failed Intel acquisition attempt (2017) and limited cloud AI traction highlight the gap.

The datacenter AI chip market Qualcomm is missing:

What Tenstorrent's Tensix Architecture Offers

Why sparse attention matters for LLM inference: In transformer attention mechanisms, most attention weights are near-zero (sparse) — they don't contribute meaningfully to the output. Standard GPUs compute all of these near-zero values anyway because they're optimised for dense matrix multiplication. Tenstorrent's Tensix cores skip zero-valued computations:

Tenstorrent's RISC-V architecture: Tenstorrent uses RISC-V (open instruction set architecture) rather than the Arm architecture that Qualcomm licenses. This is strategic: if acquired, Qualcomm could design future datacenter chips without Arm royalty payments (~$0.50–$1.50 per chip) and without Arm's licensing terms restricting custom modifications. For datacenter chips at volume (millions of chips), this represents significant cost savings and design freedom.

Why Jim Keller matters: Jim Keller designed: AMD K7 (saved AMD), AMD K8 (first 64-bit PC architecture), Apple A4/A5 (iPhone 4), Tesla Autopilot chip, AMD Zen (the architecture that brought AMD back to parity with Intel), and Intel's Meteor Lake architecture. He is arguably the most influential chip architect of the past 30 years. Acquiring Tenstorrent effectively acquires Keller.

---

⚡ Coherent CHIPS Act — The Optical Interconnect Revolution

Why Copper Cables Are Failing Inside AI Data Centres

The "memory wall" (compute outpacing memory bandwidth) is well-known. A less-discussed bottleneck: the communication wall — the copper cables connecting GPUs inside AI training clusters hitting their physical limits.

Copper vs optical interconnect comparison:

In an Nvidia GB200 NVL72 rack (72 GPUs), there are ~2,160 copper cables running between GPUs and NVLink switches. Each cable dissipates heat. At rack-scale, cable thermal dissipation is now a significant data centre cooling burden.

Indium Phosphide (InP) — why it's essential for optical chips:

Silicon doesn't emit light efficiently (indirect bandgap). Indium Phosphide (InP) has a direct bandgap — it lases efficiently and is used for:

• High-speed laser diodes (1310nm and 1550nm — standard telecom/datacom wavelengths)
• Electro-absorption modulators (modulate data onto laser at 400+ Gb/s rates)
• Photodetectors (receive optical signals)

Coherent's CHIPS Act funding:

US InP supply dependency before this investment: ~70% of InP wafers consumed by US AI data centre equipment came from Asian manufacturers (primarily Japan, Taiwan, and China). The Coherent expansion reduces this to ~45% by 2028.

---

🤖 SigmanticAI — Agentic RTL Design Automation

The Chip Design Talent Crisis

The semiconductor engineer shortage (2026):

This shortage is the primary reason that only the largest companies (Nvidia, Apple, Google, Amazon) can afford custom silicon. SigmanticAI's thesis: AI can do 60–80% of the RTL design work, allowing smaller teams to compete.

The SigmanticAI Multi-Agent Architecture

The standard RTL design workflow (before SigmanticAI):

1. Hardware specification (written by humans): "Design a 4-stage pipeline 32-bit RISC-V integer core with branch prediction"
2. RTL code (Verilog/SystemVerilog): ~50,000–200,000 lines of code per complex block
3. Testbench (UVM): ~100,000–500,000 lines of verification code per block
4. Compilation: Synopsys VCS or Cadence Xcelium runs simulation
5. Coverage analysis: Check if all corner cases were exercised
6. Debugging: Engineers read simulation waveforms and logs to identify bugs
7. Fix + re-simulate: Repeat steps 4–7 (typically 50–200 iterations per block)

SigmanticAI's multi-agent system:

SigmanticAI's performance claims (internal benchmark, published June 2026):

Caveats: these benchmarks are for designs that meet functional correctness (all simulations pass). Physical design (timing closure, place-and-route) and silicon validation still require human engineers post-SigmanticAI.

---

📌 The Bottom Line

• qualcomm-tenstorrent-risc-v-acquisition: $8-10B acquisition talks; Tensix sparse attention advantage: 80% sparsity → 800 vs 312 TFLOPS effective, 2.2× LLM throughput, 2.5× power efficiency; RISC-V = eliminates Arm royalties ($0.50-1.50/chip) + full design freedom; Jim Keller track record: AMD K7/K8/Zen, Apple A4/A5, Tesla Autopilot, Intel Meteor Lake; fills Qualcomm's 0% datacenter AI market share vs Nvidia's 88%.
• coherent-inp-chips-act-optical: Copper wall: 400 Gb/s limit, 3-5m reach, 5-10 pJ/bit, high thermal; silicon photonics: 3.2-6.4 Tb/s, 10km, <1 pJ/bit; InP required (direct bandgap lases efficiently); $50M CHIPS Act + $50M+ matching; Sherman TX: 5K → 15K InP wafer starts/month; US dependency 70% → 45% Asian InP supply; targets: 400G/800G/1.6T transceiver PICs for AI clusters; online Q2 2028.
• sigmantic-ai-rtl-agent: 230K engineer shortfall (36% gap); $195K/year US RTL engineer; 24-48 month ASIC design cycle; 7-agent system: Director + RTL Writer + Testbench + Compile Monitor + Debug + Fix + Coverage; tool integration: VCS/Xcelium/Synopsys APIs; benchmarks: 32-bit RISC-V 6-9 months → 8 days (95%); LLM accelerator 12-18 months → 21 days (97%); limitation: physical design (timing closure, P&R) still needs humans post-RTL.

---

📬 Stay Updated

Get the best of AI & technology delivered to your inbox every week. Subscribe to our free newsletter →

---

Disclosure: This post contains affiliate links. If you purchase through our links, we earn a small commission at no extra cost to you. We only recommend products we believe in.